This invention relates to semiconductor memory devices, and more particularly to an N-channel silicon gate MOS read only memory and a process for making it.
Storage of fixed programs in digital equipment such as minicomputers and microprocessor systems is usually provided by MOS read only memory devices or "ROMs". The economics of manufacture of semiconductor devices such as ROMs, and of mounting them on circuit boards in the system, are such that the number of memory bits per semiconductor chip is advantageously as high as possible. ROMs of up to 32K bits (32,768) are typical at present. Within a few years, standard sizes will progress through 64K, 128K, 256K and 1 megabit. This dictates that cell size for the storage cells of the ROM be quite small. Metal gate ROMs of small size can be relatively easily fabricated in the manner set forth in U.S. Pat. No. 3,541,543, assigned to Texas Instruments, but usually these are programmed by the gate level mask which is at an early stage in the process. Most microprocessor and computer parts are now made by the N-channel silicon gate process because of the shorter access times provided. In the past, the N-channel process has not been favorable to layout of ROM cells of small size and/or programming has been by the moat mask, also early in the manufacturing process. N-channel ROMs are disclosed in prior applications Ser. Nos. 762,612, filed Jan. 29, 1977 and 701,932, filed July 1, 1976, 890,555, 890,556 and 890,557, filed Mar. 20, 1976, all assigned to Texas Instruments. A series ROM and method of programming is shown in U.S. Pat. No. 4,059,826 to Gerald D. Rogers, assigned to Texas Instruments. Previous cells programmed at the metal level mask were by contact areas between metal lines and polysilicon gates, or by contacts between metal lines and N+ source or drain regions, used excessive space on the chip because a separate area was used for no other purpose than the contact.
It is the principal object of this invention to provide a semiconductor device such as a permanent store memory cell of small size. Another object is to provide a small-area memory cell which is made by a process compatible with standard double level poly N-channel silicon gate manufacturing techniques.